1. Field of the Invention
This invention relates to error detection codes, and more particularly, to error detection codes that detect component failures and up to three arbitrary bit errors.
2. Description of the Related Art
Error detection codes are commonly used in electronic systems to detect data errors, such as transmission errors or storage errors. For example, error detection codes may be used to detect errors within data transmitted via a telephone line, a radio transmitter or a compact disc laser. One common use of error detection codes is to detect errors within data that are stored or read from a memory of a computer system. For example, error detection bits, or check bits, may be generated for data prior to storing data to one or more memory devices. When the data are read from the memory device, the check bits may be used to detect errors within the data. Errors may be introduced either due to faulty components or noise within the computer system. Faulty components may include faulty memory devices or faulty data paths between devices within the computer system, such as faulty pins.
Parity checking is a commonly used technique for error detection. A parity bit, or check bit, is added to a group of data bits. The check bit may be asserted depending on the number of asserted data bits within the group of data bits. If even parity is used, the check bit will make the total number of asserted bits, including the data bits and the check bit, equal to an even number. If odd parity if used, the check bit will make the total number of asserted bits, including the data bits and the check bit, an odd number. Parity checking is effective for detecting an odd number of errors. If an even number of errors occurs, however, parity checking will not detect the error.
More complex error detection codes, such as Hamming codes, may be used to detect multiple bit errors. Unfortunately, these more complex error detection codes typically require a significant number of additional bits. It is a common design goal of computer systems to reduce the number of check bits used to detect errors. The check bits increase the amount of data handled by the system, which may increase the number of memory components, data paths and other circuitry. Further, the increased amount of data increases the probability of an error. Although the check bits may make an error detectable, increasing the amount of data within the system increases the probability of an error occurring. For at least the above reasons, it is desirable to decrease the number of check bits for a given level of error detection.
What is desired is an error detection technique that detects multiple bit errors, including even multiple bit errors, with the same number of check bits as parity checking. It is further desirable to detect a component failure in a memory system employing the error detection scheme.